(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of preventing silicon pits in the active region in the fabrication of integrated circuits.
(2) Description of the Prior Art
As device sizes shrink into the sub-micron and sub-half-micron regime, it has become necessary to use a combination of polysilicon and refractory metal silicides as the material for gate electrodes and interconnection lines because of their reduced resistivity. It is also essential to keep the active regions as free from defects as possible. Pitting of the silicon in the active areas can cause junction leakage and low yields. FIG. 1 illustrates a partially completed integrated circuit device in which voids 20 form at the interface between a polysilicon layer 16 and a silicide layer 18 after deposition of a tetraethoxysilane (TEOS) layer 19. When the polysilicon and silicide layers are patterned to form a gate electrode, as illustrated in FIG. 2, pits 22 are formed in the silicon where the voids were located.
Workers in the art have used thermal annealing in the manufacture of integrated circuit devices. U.S. Pat. No. 5,393,685 to Yoo et al uses thermal annealing at greater than 1000.degree. C. after gate patterning to prevent peeling of an overlying tungsten silicide layer. U.S. Pat. No. 4,833,099 to Woo forms double oxide spacers on a gate electrode, reoxidizes them to form horns, then anneals the structure. U.S. Pat. No. 5,434,096 to Chu et al anneals after gate patterning at 800.degree. C., then ramps up to 900.degree. C. for outgassing. U.S. Pat. No. 5,472,896 to Chen et al and U.S. Pat. No. 5,605,854 to Yoo disclose other polycide processes. None of these workers describe a solution to the silicon pitting problem described above.
The paper, "Oxidation Phenomena of Polysilicon/Tungsten Silicide Structures," by N. Hsieh, Journal of the Electrochemical Society, January 1984, pp. 201-205, discusses the formation of voids in a polysilicon layer under a silicide layer. The voids form as a result of pinholes in the native oxide layer between the polysilicon and the silicide layers. In the paper, "Controlling Void Formation in WSi.sub.2 Polycides," by C. W. Koburger et al, IEEE Electron Device Letters, Vol. EDL-5, No. 5, May 1984, pp. 166-168, the authors also discuss void formation in the polysilicon layer under a silicide layer. They prevent the formation of these voids by depositing a capping layer of polysilicon over the silicide prior to oxidation.